User manual Analog Devices TigerSHARC ADSP-TS201S

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TigerSHARC®  
a
Embedded Processor  
ADSP-TS201S  
KEY FEATURES  
KEY BENEFITS  
Up to 600 MHz, 1.67 ns instruction cycle rate  
Provides high performance static superscalar DSP  
operations, optimized for telecommunications  
infrastructure and other large, demanding multiprocessor  
DSP applications  
2
4M bits of internal—on-chip—DRAM memory  
5 mm × 25 mm (576-ball) thermally enhanced ball grid  
array package  
2
Performs exceptionally well on DSP algorithm and I/O  
benchmarks (see benchmarks in Table 1)  
Supports low overhead DMA transfers between internal  
memory, external memory, memory-mapped peripherals,  
link ports, host processors, and other  
Dual-computation blocks—each containing an ALU, a  
multiplier, a shifter, a register file, and a communications  
logic unit (CLU)  
Dual-integer ALUs, providing data addressing and pointer  
manipulation  
Integrated I/O includes 14-channel DMA controller, external  
port, four link ports, SDRAM controller, programmable  
flag pins, two timers, and timer expired pin for system  
integration  
(multiprocessor) DSPs  
Eases DSP programming through extremely flexible instruc-  
tion set and high-level-language-friendly DSP architecture  
Enables scalable multiprocessing systems with low commu-  
nications overhead  
1149.1 IEEE-compliant JTAG test access port for on-chip  
emulation  
Provides on-chip arbitration for glueless multiprocessing  
Single-precision IEEE 32-bit and extended-precision 40-bit  
floating-point data formats and 8-, 16-, 32-, and 64-bit  
fixed-point data formats  
DATAADDRESSGENERATION  
24MBITSINTERNALMEMORY  
SOCBUS  
JTAGPORT  
6
32  
32  
INTEGER  
JALU  
INTEGER  
KALU  
MEMORYBLOCKS  
(PAGECACHE)  
JTAG  
EXTERNAL  
PORT  
3
2-BIT×32-BIT  
32-BIT×32-BIT  
4×CROSSBARCONNECT  
PROGRAM  
SEQUENCER  
32  
A
A
A
A
D D  
D
D
ADDR  
J-BUSADDR  
J-BUSDATA  
K-BUSADDR  
K-BUSDATA  
I-BUSADDR  
I-BUSDATA  
32  
HOST  
ADDR  
FETCH  
64  
8
MULTI-  
PROC  
128  
DATA  
CTRL  
CTRL  
SDRAM  
CTRL  
32  
10  
BTB  
C-BUS  
ARB  
128  
SOC  
I/F  
32  
EXTDMA  
REQ  
4
128  
DMA  
PC  
LINKPORTS  
4
S-BUSADDR  
S-BUSDATA 128  
21  
IN  
8
4
8
4
L0  
L1  
L2  
L3  
OUT  
IAB  
T
IN  
8
4
8
4
OUT  
IN  
8
4
8
4
1
28  
128  
128  
OUT  
X
Y
REGISTER  
FILE  
IN  
8
4
8
REGISTER  
FILE  
2-BIT×32-BIT  
128  
CLU  
SHIFT ALU MUL  
MUL ALU SHIFT  
CLU  
DAB DAB  
OUT  
3
32-BIT×32-BIT  
COMPUTATIONALBLOCKS  
Figure 1. Functional Block Diagram  
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.  
Rev. C  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2006 Analog Devices, Inc. All rights reserved.  

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