User manual Fujitsu MB15E07SL

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When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.  
: When the LPF and VCO characteristics are similar  
to (1), set FC bit high.  
: When the VCO characteristics are similar to (2), set  
FC bit low.  
LPF Output Voltage  
3. Do Output Control  
Table 9. ZC Pin Setting  
ZC pin  
Do output  
Normal output  
High impedance  
. Power Saving Mode (Intermittent Mode Control Circuit)  
Table 10. PS Pin Setting  
PS pin  
Normal mode  
Power saving mode  
The intermittent mode control circuit reduces the PLL power consumption.  
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See  
the Electrical Characteristics chart for the specific value.  
The phase detector output, Do, becomes high impedance.  
For the signal PLL, the lock detector, LD, remains high, indicating a locked condition.  
Setting the PS pin high, releases the power saving mode, and the device works normally.  
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.  
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is  
of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can  
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup  
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error  
signal from the phase detector when it returns to normal operation.  
When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 µs.  

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