User manual Fujitsu MB15E07SL

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MB15E07SL  
SERIAL DATA INPUT TIMING  
1st data  
2nd data  
Control bit Invalid data  
Data  
MSB  
LSB  
Clock  
t
1
t
2
t3  
t
6
t
7
LE  
t
4
t5  
On the rising edge of the clock, one bit of data is transferred into the shift register.  
Parameter Min  
Typ  
Max Unit  
Parameter Min  
Typ  
Max Unit  
t
t
t
t
1
2
3
4
20  
20  
30  
30  
ns  
ns  
ns  
ns  
t5  
t6  
t7  
100  
20  
ns  
ns  
ns  
100  
Note : LE should be “L” when the data is transferred into the shift register.  
13  

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