User manual NXP Semiconductors TFA9812

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TFA9812  
BTL stereo Class-D audio amplifier with I2S input  
Rev. 02 — 22 January 2009  
Preliminary data sheet  
1. General description  
The TFA9812 is a high-efficiency Bridge Tied Load (BTL) stereo Class-D audio amplifier  
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with a digital I S audio input. It is available in a HVQFN48 package with exposed die  
paddle. The exposed die paddle technology enhances the thermal and electrical  
performances of the device.  
The TFA9812 features digital sound processing and audio power amplification. It supports  
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I C control mode and Legacy mode. In Legacy mode I C involvement is not needed  
because the key features are controlled by hardware pin connections.  
A continuous time output power of 2 × 12 W (RL = 8, VDDP = 15 V) is supported without  
an external heat sink. Due to the implementation of a programmable thermal foldback  
even for high supply voltages, higher ambient temperatures, and/or lower load  
impedances, the device operates without sound interrupting behavior.  
TFA9812 is designed in such a way that it starts up easily (no special power-up sequence  
required). It features various soft and hard impact protection mechanisms to ensure an  
application that is both user friendly and robust.  
A modulation technique is applied for the TFA9812, which supports common mode choke  
approach (1 common mode choke only per BTL amplifier stage). This minimizes the  
number of external components.  
2. Features  
2.1 General features  
I 3.3 V and 8 V to 20 V external power supply  
I High efficiency and low power dissipation  
I Speaker outputs fully short circuit proof across load, to supply lines and ground  
I Pop noise free at power-up/power-down and sample rate switching  
I Low power Sleep mode  
I Overvoltage and undervoltage protection on the 8 V to 20 V power supply  
I Undervoltage protection on the 3.3 V power supply  
I Overcurrent protection (no audible interruptions)  
I Overdissipation protection  
I Thermally protected and programmable thermal foldback  
I Clock error protection  
I I2C mode control or Legacy mode (i.e. no I2C) control  
I Four different I2C addresses supported  
I Internal Phase-Locked Loop (PLL) without using external components  

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